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Re: CMUCL's kernel requirements
Viz signal codes. I see there are various minor but significant
differences in mips/trap.c and mips/mips_exception.c in CS7 viz latest.
The code in latest is the correct one, e.g. it does the same thing that
Viz sigcontext. There is a catch viz exceptions that happen in the
branch delay slot of an instruction. It is described in the Ultrix
man page for signals, and other man pages for special functions that
are part of libc (all this from MIPSco). It is quite possible that Rob
saw one of these cases. I am about to put this and other man pages in
the /usr/misc/.ultrix collection that mja has freshly set up.
This has no impact on the kernel.
> But what about the Pmax? It has seperate I&D caches, but they are
> write-through. After we create a code object using the data cache, do
> we have to do anything to make sure we can execute it?
An I-cache is not "writeable" (all stores go through the D-cache),
if it contains a cached instruction located at ADDR and you modify
the content of ADDR the Icache will happily continue to use its cached
value until that cache entry gets replaced by an instruction located
at some other colliding address ADDR1. Or if you flush the cache.
The answer to your question is therefore YES, unless you can be
absolutely sure there are no entries in the Icache for that page
you are touching you should flush the Icache, just in case.
Viz VM paging performance. If memory serves, I measured a 30% (or was
it a 50%?) speedup in that large compilation test I was using (setq.lisp
from the lisp sources). Whether people will notice or not depends on
their paging behaviour.
Hope this helps,