Re: CMUCL's kernel requirements

[William.Lott@CS.CMU.EDU]

Alessandro.Forin@SPICE.CS.CMU.EDU writes:
> > But what about the Pmax?  It has seperate I&D caches, but they are
> > write-through.  After we create a code object using the data cache, do
> > we have to do anything to make sure we can execute it?
> 
> An I-cache is not "writeable" (all stores go through the D-cache), 
> if it contains a cached instruction located at ADDR and you modify
> the content of ADDR the Icache will happily continue to use its cached
> value until that cache entry gets replaced by an instruction located
> at some other colliding address ADDR1.  Or if you flush the cache.
> The answer to your question is therefore YES, unless you can be
> absolutely sure there are no entries in the Icache for that page
> you are touching you should flush the Icache, just in case.

We only create code objects in virgin memory (i.e. has not been
touched in any way after the last vm_allocate).  Therefore, if
vm_allocate flushes the allocated range from the various caches, we
don't need to do any additional flushing.  Does it do this?  (Seems to
me like it would have to.)

-William